PDS – Parallel and Distributed Systems track

Master of computer science
// 2 or 3 subjects from Petr // TODO 3 subjects from Nico

Research project (2025/2026)

During the master, a student will learn research by doing research. During the two years of the master, a student will thus spend between one or two days each week in a research group in order to do research projects with professors and PhD students of IP Paris.

You can find last year's project here

Research project schedule

When Where What
19/09/2025 at 10h00 Telecom Paris, (room: 1A312) and online Presentation of project proposals
29/09/2025 Project starts
6/03/2026 TBD Report and final evaluation for M2 students, mid-term for M1 students
26/06/2026 TBD Report and final evaluation for M1 students

Project Evaluation

Research projects will be evaluated on a research report, and a presentation. The project defense is a 20 minutes presentation of the research work followed by 5-10 minutes of questions. The presentation has to explain the work context and problematics, and describe the contribution of the conducted research project.

The report is a expected to be a 5 to 8 pages research paper formatted using the ACM conference style. The report should present the context of the work, its contribution, a positioning with respect to related works. Both M1 and M2 students are expected to send their research report by email by friday, 6/3/2025. M1 students are expected to update their report and resubmit it in june.

Project defense schedule

The project defense will take place Palaiseau or online at this address. Attending the other students presentation is not mandatory, but it would be appreciated.

Time Room Student Project Advisors

Proposed projects

The following project proposals may be shared with several masters track, including DataAI, HPDA, PDS, Cybersecurity, or CPS.

Id Title Advisors Location Description Student
1 Verification of the Linux kernel xarray library Julia Lawall Inria Paris, Paris Corinn Tiffany
2 Addition of peripherals on the CVA6 core using HLS Nicolas Derumigny Telecom building, Palaiseau Description
3 Customization of the CVA6 core Nicolas Derumigny Telecom building, Palaiseau Description
4 MARS Attack: Optimizing CPU to FPGA data transfers through coalescing, compression and data layout reordering Nicolas Derumigny Telecom building, Palaiseau Description