Interrupts and communication

Gaël Thomas

Mathieu Bacou

Communication buses

Communication buses

The memory bus

DMA: Direct Memory Access

MMIO: Memory-Mapped IO

The input / output bus

The interrupt bus - principle


Receiving an interrupt: simple routing

Receiving an interrupt: example

  1. A block device on IRQ line 0X14 signals a data block is available
  2. The PLIC reads the configured priority of IRQ 0x14: 0x2
  3. The PLIC signals all processors with priority threshold \(<\) 0x2
  4. All signaled processors compete to serve the interrupt

Interrupt routing in NUMA architectures

In Non Uniform Memory Access architectures (NUMA), a device is linked to only one NUMA node. On RISC-V architectures, this means a device is linked to only one PLIC, as there is one PLIC per NUMA node. So only a processor from this NUMA node can serve interrupts from this device.

Interrupt routing on x86 architecture

On x86, interrupt routing goes through two tables configured by the kernel:

  1. Routing table: associates an IRQ with an IDT number
  2. IDT table (interrupt descriptor table): associates an IDT number to a interrupt handler

Two tables allow more flexibility than a single table which associates an IRQ number directly with a manager. This is different from RISC-V architecture where there can only be one interrupt handler, that must check the kind of the interrupt to serve it (e.g., a device interrupt, a timer interrupt, etc.).

Example of routing:

This is with only one processor; on multicore x86 systems:

Receiving an interrupt: simple routing (continued)

MSI: Message Signaling Interrupt for advanced interrupt management

MSIs and PLIC in RISC-V architectures

The PLIC (usually an APLIC, Advanced PLIC) remains used by devices that do not (need to) support MSI. When the platform supports MSIs, the APLIC converts wired (i.e., non message signaled) interrupts into MSIs. This is configured by the OS, as if they were direct MSIs from external devices.

MSIs on x86

On x86 systems, MSIs work roughly the same:

Inter-core communication

IPIs on x86 architectures

Other interruptions: system calls and exceptions

On x86 systems, the IDT table is used for every possible interruption:

The IDT table is therefore the table that contains all of the entry points to the kernel:

Time management: two sources